Capture The Bug

A Design Verification Hackathon
using Vyoma's UpTickPro tool
to build skilled engineers delivering high quality semiconductor designs



Online and Cloud based


15th July to 1st Aug, 2022

Registration till 13th July, 2022

About Capture The Bug Hackathon

To provide a basic hands-on for design verification, which enhances practical verification knowledge. The verification challenge helps to understand the verification intent to detect bugs in designs, understand debugging and fix the buggy designs. It provides a practical exposure to real world design verification activities

The hackathon aims to generate skilled manpower in the domain of Design Verification, which will strengthen the quality of designs being manufactured. It reduces chip failure, improving the time to market cycle of Semiconductor products.

The Indian government initiative Chips to Startup (C2S) programme aims to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a semiconductor ecosystem that requires 85,000+ highly trained engineers. Working towards this vision statement, we have planned the 3-Week “Capture the Bug” , a Design Verification Challenge.
This Hackathon is organized by NIELIT Calicut and technically facilitated by Vyoma Systems , VLSI System Design & IEEE Robotics and Automation Society and ably mentored by Indian Institute of Technology Madras (IIT Madras).

Who can participate?

  • Only individual participants (no group)
  • FREE Registration & Participation
  • Basic Digital Design Knowledge expected
  • Open to all verification enthusiasts, students and working professionals

Hackathon Schedule

Participants Registration Link

Hackathon Inauguration Webinar

NIELIT, Vyoma and VSD will introduce participants to the design verification challenge

Hackathon Screening

To participate in the hackathon, the participants need to identify any open source design and understand their design and implementation details

Screening Report Submission

Participants need to submit their understanding of their chosen design as a report.

Capture The Bug Hackathon

Participants will use Vyoma’s UpTickPro verification platform to detect the bugs in the given designs

Final Report Submission

Participants need to upload the verification environment in Python that finds the bugs and also document the debugging information

CTB Results & Closing Webinar

Result Declaration and Announcements

CTB Results

Great Work CTB Champions!

Soumitro Vyapari

IIT Tirupati

Navinkumar Kanagalingam

Puducherry Technological University

Satya Rajesh Medidi


Tanuj Sindhwani

Siemens EDA

Aishwarya Balkrishna Patil

Kolhapur Institute of Technology College of Engineering, Kolhapur

Shaik Yousuf

NIT Tiruchirappalli

Mohitha Kondapalli

TechMahindra Cerium

Vivek Nair

IIT Palakkad

Neha Singh

Siemens EDA

Raffaele Signoriello


Mohammed Shafi Ur Rehman

National Institute of technology Tiruchirapalli

Shirsendu B Acharyya


Tushar Upadhyay

Manipal Institute of Technology

Rishabh Verma

Zakir Husain College of Engineering & Technology, Aligarh Muslim University

Preethaa J

College of Engineering, Guindy, Anna University

Jayaraman R P


Thilak Kuppusamy

Madras Institute of Technology

Darshan Datta Naik

RV College of Engineering , Bengaluru

Pramit Kumar Pal

Techno International Newtown, MAKAUT

Victor Swaroop G


Hrishikesh Badiger

KLE Technological University

Pavan Dheeraj

SSN College of Engineering

Elavarasan P

Madras Institute of Technology

Abhishek Das

Birla Institute Of Technology And Science, Pilani

K Aditya Sai

Indian Institute of Technology, Bhubaneswar

Arpit Sharma

Inderprastha Engineering College [IPEC]

Vinayak Prakash Mali

Kolhapur Institute of Technology's College of Engineering, Kolhapur

Vinisha R

Madras Institute of Technology, Anna University

Greeshmanth Nadella

Infineon Technologies

Mustafa Mohamed Abdelhamid

Faculty of Engineering, Cairo University

Krunal Badlani

Indian Institute of Technology Hyderabad

Arka Chakraborty

Jadavpur University

Krishna Gupta

Jaypee Institute of Information Technology

Kevin Prakash

BIT Pilani

Tanay Das

Sikkim Manipal Institute of Technology

Souhardhya Paul


Ch Kalyan Kumar Prusty


Karan Sanghavi

Sardar Patel Institute Of Tehnology

Vaikunth guruswamy

Madras Institute of Technology, Anna University

Surya V

IIITDM Kanchepuram

Lahari Sreeja Tallapaka

Indian Institute of Technology - Bhilai (IIT Bhilai)

Mohamed Adel Mohamed Hassan

Cairo University


K.J Somaiya College of Engineering

Paripati Yeshwanth

Synopsys India Pvt. Ltd.

Garv Jain

Indian Institute of Technology Patna

Thomas M Josline

Indian Institute of Technology, Bhilai

Sheshu Ramanandan

Smartray GmbH

Tanya Tyagi


Nikhil Dewangan

Shri Shankaracharya Group of Institutions

Kolluru Yashwanth

IIIT Ranchi

Anvay Pancholiya

RV College of Engineering

Santanu Samanta

Heritage Institute of Technology

R Abhinav

Madras institute of technology

Amreen Kaur

Indian Institute of Technology, Hyderabad

Diwakar B

MIT, Chennai

Narra Hemanth Reddy

JNTUH College of Engineering, Hyderabad

Ritvik Rao

Birla Institute of Technology and Science, Pilani Campus

Karthik Mahendra Kumar Banakar

Modernize Chip Solutions Pvt Ltd

Toushik Santra


Ashwanth G

Dr. N. G. P. Institute of technology

Sameer Yadav


Puneeth Kamatham

Lovely Professional University

Manoj SReddy

K. J. Somaiya College of Engineering

Madala Changala Naga Lakshmi Neha

DR.B.R.Ambedkar National Institute of Technology, Jalandhar

Divyanshu Pandey


Lakshmi Padmaja Rongali


Avishke Choudhary

Thapar Institute of Engineering and Technology

Prajval S Vadakannavar


Mihir Rana

Nirma University

Jenish Shah

IIT Indore

Sree Ranjani Rajendran

University of Florida

Chaitanya Chhichhia

Institute of Technology, Nirma University


K.L University (Guntur)

Jeenang Shah

Micron Technology Operations India LLP

Anushka Subramanian


Shreyas M


Emmanuel Innocent

Obafemi Awolowo University





Khoushikh S

Infineon Technologies

Rohith Reddy Appidi


Darisa Vinuthna Sri

IIIT Dharwad

Sudhanshu Singh

Indian Institute of Technology Patna

Sidhant Priyadarshi

KLE technological University

Vijaykumar Sajjanar


Chhaya Belwal

Netaji Subhas University of Technology, Delhi

Keerthana Madhusoodan

Kongu Engineering College

Yajnesh K

Mangalore Institute of Technology and Engineering

Animesh Jana

National Institute of Technology Calicut

Yash Tomar

Vervesemi microelectronics

Mohit Agarwal K

Nirma University

Sajja Pratyusha



SRM University

Pranav Prabhu

Manipal Institute of Technology,Manipal

Madhuri H Kadam

Shree L. R. Tiwari College of Engineering

A Devipriya

Trainee at VSD and SFAL

Aakash K

Trainee at VSD and SFAL



Subha Ratno Das

Jadavpur University

Soni Harshil

Birla Vishvakarma Mahavidyalaya


Thiagarajar College of Engineering

Zaid Akhtar

Aligarh Muslim University

Maharshi Soni

Birla Vishwakarma Mahavidyalaya(B.V.M)

Prajwal D Nayak

PES University

Haritha Gopisetty

Gayatri Vidya Parishad College of Engg(Autonomous)

Akshaya Adlakha

Amity University, Noida

Jayanth Nedunuri

Jyothishmathi Institute of Technology and Science


SASTRA Deemed University


Tech Mahindra Cerium Systems Private Limited

Siddharth Sahu


Nanubolu Ravi Kumar

Nitte Meenakshi Institute Of Technology

P Akhil Reddy

Koneru Lakshmaiah University(Klu)

Jay S Kaku

University of Mumbai / Thadomal Shahani Engineering College



Aishik Das

Larson and Tourbo

Gaeya Sri Satya Vinnakota

Sardar Vallabhbhai National Institute Of Technology

Mahima Goyen

Texas AnM University

Tejaswini S

H.K.B.K College Of Engineering

Ravi Mugidi

Rajiv Gandhi University of Knowledge and Technologies(RGUKT) Srikakulam

Nagamallishwar N

Indian Institute of Information Technology, Tiruchirappalli

Vanshika Tanwar

Dronacharya Group Of Institutions, Greater Noida


System Requirements

  • The minimum requirements for running the tool are the following
  • Any OS
  • Firefox/Chrome Browser has been tested
  • Min 4 Mbps internet connection
  • Minimum of 2GB RAM on Laptop/PC

Tool Used

  • Vyoma’s UpTickPro Platform caters to the next generation semiconductor needs for rapid design verification spanning various design complexities
  • It is a verification-as-a-service platform that leverages state-of-the-art cloud compute and verification methodology
  • Straightforward to use to quickly develop your Python based design verification environment

Problem Statement

To use the verification platform provided and expose all the bugs in the designs. It involves writing test scenarios in Python to capture the bugs in the given designs.

Terms & Conditions

  • The design simulation has to be done only using Vyoma’s UpTickPro Platform
  • The tests are to be submitted in Python only and the submission guidelines have to be followed
  • This hackathon is open only to individuals. We will not accept team or group registration/submissions
  • Any participant found to be indulging in any form of malpractice will be immediately disqualified
  • The decision of the review committee and the organizers in declaring the results will be final. No queries in this regard will be entertained



  • Yes, participation is free for all. We would like to have the active involvement of students and professionals in the VLSI verification domain and hence the motivation. You are, however, required to provide your correct information for identification purposes during the registration process.

  • On completion of registration, participants will be given an overview of design verification. The screening process requires the participants to choose a Verilog Design of their own, understand its implementation and submit a report detailing the design and verification strategy. Only participants successfully completing the report will be provided with the Design Verification Challenges.

  • On completion of registration, participants will be given an overview of design verification and the setup required for the hackathon. As part of the hackathon, you will be required to develop Python test cases in the setup provided to identify design bugs at 3 complexity levels. More information and support will be provided as part of the hackathon.

    • Design Level 1: Simple combinational and sequential circuits
    • Design Level 2: A more complex compute block
    • Design Level 3: A Design chosen by the Participant
  • Yes, absolutely! The hackathon is developed in such a way that very minimal basic of Python and Verilog are required. Design or verification knowledge would be helpful. However, all that is required is the attitude to want to learn independently, try out new challenges and have fun in the process.

    • Get a basic understanding of the semiconductor industry and verification flow.
    • Get a hands-on experience on the verification activities. Have an understanding of design verification as a career path.
    • Get an e-certificate on successful completion of screening as well as the CTB verification challenges.


Technical Facilitators