Capture The Bug

A Design Verification Hackathon
using Vyoma's UpTickPro tool
to build skilled engineers delivering high quality semiconductor designs

Register

HOW

Online and Cloud based

When

15th July to 1st Aug, 2022

Registration till 13th July, 2022

About Capture The Bug Hackathon

To provide a basic hands-on for design verification, which enhances practical verification knowledge. The verification challenge helps to understand the verification intent to detect bugs in designs, understand debugging and fix the buggy designs. It provides a practical exposure to real world design verification activities

The hackathon aims to generate skilled manpower in the domain of Design Verification, which will strengthen the quality of designs being manufactured. It reduces chip failure, improving the time to market cycle of Semiconductor products.

The Indian government initiative Chips to Startup (C2S) programme aims to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a semiconductor ecosystem that requires 85,000+ highly trained engineers. Working towards this vision statement, we have planned the 3-Week “Capture the Bug” , a Design Verification Challenge.
This Hackathon is organized by NIELIT Calicut and technically facilitated by Vyoma Systems , VLSI System Design & IEEE Robotics and Automation Society and ably mentored by Indian Institute of Technology Madras (IIT Madras).

Who can participate?

  • Only individual participants (no group)
  • FREE Registration & Participation
  • Basic Digital Design Knowledge expected
  • Open to all verification enthusiasts, students and working professionals

Hackathon Schedule

Participants Registration Link

Hackathon Inauguration Webinar

NIELIT, Vyoma and VSD will introduce participants to the design verification challenge

Hackathon Screening

To participate in the hackathon, the participants need to identify any open source design and understand their design and implementation details

Screening Report Submission

Participants need to submit their understanding of their chosen design as a report.

Capture The Bug Hackathon

Participants will use Vyoma’s UpTickPro verification platform to detect the bugs in the given designs

Final Report Submission

Participants need to upload the verification environment in Python that finds the bugs and also document the debugging information

CTB Results & Closing Webinar

Result Declaration and Announcements

Resources

System Requirements

  • The minimum requirements for running the tool are the following
  • Any OS
  • Firefox/Chrome Browser has been tested
  • Min 4 Mbps internet connection
  • Minimum of 2GB RAM on Laptop/PC

Tool Used

  • Vyoma’s UpTickPro Platform caters to the next generation semiconductor needs for rapid design verification spanning various design complexities
  • It is a verification-as-a-service platform that leverages state-of-the-art cloud compute and verification methodology
  • Straightforward to use to quickly develop your Python based design verification environment

Problem Statement

To use the verification platform provided and expose all the bugs in the designs. It involves writing test scenarios in Python to capture the bugs in the given designs.

Terms & Conditions

  • The design simulation has to be done only using Vyoma’s UpTickPro Platform
  • The tests are to be submitted in Python only and the submission guidelines have to be followed
  • This hackathon is open only to individuals. We will not accept team or group registration/submissions
  • Any participant found to be indulging in any form of malpractice will be immediately disqualified
  • The decision of the review committee and the organizers in declaring the results will be final. No queries in this regard will be entertained

Poster

F.A.Q

  • Yes, participation is free for all. We would like to have the active involvement of students and professionals in the VLSI verification domain and hence the motivation. You are, however, required to provide your correct information for identification purposes during the registration process.

  • On completion of registration, participants will be given an overview of design verification. The screening process requires the participants to choose a Verilog Design of their own, understand its implementation and submit a report detailing the design and verification strategy. Only participants successfully completing the report will be provided with the Design Verification Challenges.

  • On completion of registration, participants will be given an overview of design verification and the setup required for the hackathon. As part of the hackathon, you will be required to develop Python test cases in the setup provided to identify design bugs at 3 complexity levels. More information and support will be provided as part of the hackathon.

    • Design Level 1: Simple combinational and sequential circuits
    • Design Level 2: A more complex compute block
    • Design Level 3: A Design chosen by the Participant
  • Yes, absolutely! The hackathon is developed in such a way that very minimal basic of Python and Verilog are required. Design or verification knowledge would be helpful. However, all that is required is the attitude to want to learn independently, try out new challenges and have fun in the process.

    • Get a basic understanding of the semiconductor industry and verification flow.
    • Get a hands-on experience on the verification activities. Have an understanding of design verification as a career path.
    • Get an e-certificate on successful completion of screening as well as the CTB verification challenges.

Organizer

Technical Facilitators

Mentors